High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors

Hiroshi TAKAHASHI  Rimon IKENO  Yutaka TOYONOH  Akihiro TAKEGAMA  Yasumasa IKEZAKI  Tohru URASAKI  Hitoshi SATOH  Masayasu ITOIGAWA  Yoshinari MATSUMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E86-C   No.4   pp.589-596
Publication Date: 2003/04/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword: 
high speed,  low power,  fixed point DSP,  160 MHz,  0.18 µm,  

Full Text: PDF(1.7MB)>>
Buy this Article




Summary: 
High-speed and low-power DSPs have been developed for versatile hand set applications. The DSP contains a 16-bit fixed point DSP core with multiple buses, highly tuned instruction sets and a low-power architecture, featuring CPU power with 404.5 µ W/MHz, chip power with 2.08 mW/MHz at peak and 200 µA stand-by current and 160 MHz/160 MIPS performance by a single DSP core, and also operates at 0.68 V within the temperature range from -40C to 125C in the worst case (Weak corner) even using much higher I-off current process compared to a conventional process to obtain a faster operating frequency. In this paper, we discuss circuit design techniques to continue scaling down valuable IP cores keeping the same functionality, better speed performance, and lower power dissipation with much lower voltage operation capability. For further power reduction by DSP software, Run-time Power Control (RPC) has been demonstrated in an MP3 player using 100 MHz/100 MIPS DSP at 1.8 V, which is a real-time application running on an Internet audio evaluation module experimentally and we obtained 32-60% power reduction on various music source data.