Design and Demonstration of Pipelined Circuits Using SFQ Logic

Akira AKAHORI  Akito SEKIYA  Takahiro YAMADA  Akira FUJIMAKI  Hisao HAYAKAWA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E85-C   No.3   pp.641-644
Publication Date: 2002/03/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Superconductive Electronics)
Category: Digital Devices and Their Applications
Keyword: 
SFQ,  pipeline architecture,  parameter spread,  leakage current,  parameter optimization method,  

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Summary: 
We have designed the Half Adder (HA) circuit and the Carry Save Serial Adder (CSSA) circuit based on pipeline architecture. Our HA has the structure of a two-stage pipeline and consists of 160 Josephson Junctions (JJs). Our CSSA has the structure of a four-stage pipeline with a feedback loop and consists of 360 JJs. These circuits were fabricated by the NEC standard process. There are two issues which should be considered in the design. One is parameter spreads generated by the fabrication process and the other is leakage currents between the gates. We have introduced a parameter optimization method to deal with the parameter spreads. We have also inserted three stages of JTLs to reduce leakage currents. We have experimentally confirmed the correct operations of these circuits. The obtained bias margins were 33.1% for the HA and 24.6% for the CSSA.