For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
50 GHz Multiplexer and Demultiplexer Designs with On-Chip Testing
Lizhen ZHENG Xiaofan MENG Stephen WHITELEY Theodore Van DUZER
IEICE TRANSACTIONS on Electronics
Publication Date: 2002/03/01
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Superconductive Electronics)
Category: Digital Devices and Their Applications
superconductive digital circuits, single-flux-quantum circuit, multiplexer, demultiplexer (DMUX),
Full Text: PDF(358.5KB)
>>Buy this Article
We present the design of dual rail Data Driven Self Timed (DDST) DEMUX and MUX circuits for 50 GHz operation. The chosen current density is 6.5 kA/cm2 and simulations show good margins for speeds exceeding 50 GHz. Our previously reported dual-rail on-chip test system is also scaled up for 50 GHz operation.