VLSI Architecture and Implementation for Speech Recognizer Based on Discriminative Bayesian Neural Network

Jhing-Fa WANG  Jia-Ching WANG  An-Nan SUEN  Chung-Hsien WU  Fan-Min LI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E85-A   No.8   pp.1861-1869
Publication Date: 2002/08/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing)
Category: Implementations of Signal Processing Systems
Keyword: 
discriminative Bayesian neural network,  speech recognition,  VLSI,  

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Summary: 
In this paper, we present an efficient VLSI architecture for the stand-alone application of a speech recognition system based on discriminative Bayesian neural network (DBNN). Regarding the recognition phase, the architecture of the Bayesian distance unit (BDU) is constructed first. In association with the BDU, we propose a template-serial architecture for the path distance accumulation to perform the recognition procedure. A corresponding architecture is also developed to accelerate the discriminative training procedure. It contains the intelligent look-up table for the sigmoid function. In comparison to the traditional one-table method, the memory size reduces drastically with only slight loss of accuracy. Combining the proposed hardware accelerators with the cost efficient programmable core, we took the most out of both programmable and application-specific architectures, including performance, design complexity, and flexibility.