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A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain
Kenichi SUZUKI
Mitsuhiro TAKEDA
Atsushi KAMO
Hideki ASAI
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E85-A No.2 pp.395-398
Publication Date: 2002/02/01
Online ISSN:
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category:
Keyword:
analog-HDL,
Verilog-A,
circuit simulation,
interconnects simulation,
time/frequency transform-domain,
Full Text: PDF(755.8KB)
Summary:
This letter presents a novel application of the Verilog-A, which is a hardware description language for analog circuits, to the modeling and simulation of high-speed interconnects in time/frequency transform-domain for signal integrity problems. This modeling method with the Verilog-A language would handle the transfer function approximation and admittance matrices, which are expressed by the dominant poles and residues as used in AWE technique. Finally, it is shown that modeling and simulation of the high-speed interconnects with nonlinear terminations can be done easily.
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