For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design
Sungjae KIM Hyungwoo LEE Juho KIM
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
low power, glitch, gate sizing, buffer insertion,
Full Text: PDF(1.6MB)>>
We present an efficient heuristic algorithm to reduce glitch power dissipation in CMOS digital circuits. In this paper, gate sizing is classified into three types and the buffer insertion is classified into two types. The proposed algorithm combines three types of gate sizing and two types of buffer insertion into a single optimization process to maximize the glitch reduction. The efficiency of our algorithm has been verified on LGSynth91 benchmark circuits with a 0.5 µm standard cell library. Experimental results show an average of 69.98% glitch reduction and 28.69% power reduction that are much better than those of gate sizing and buffer insertion performed independently.