Selective Clock Suppression of Protocol Modules for a Low Power Protocol Converter

Young Moo LEE  Kyu Ho PARK  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E84-D   No.7   pp.906-909
Publication Date: 2001/07/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer System Element
Keyword: 
CMOS digital integrated circuit,  low power,  protocol conversion,  

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Summary: 
This letter presents a method for reducing power dissipation in a protocol converter. The communication protocol of a VLSI chip hierarchically consists of several sub-protocols and only one of them can be actively working at any given time. In general, protocol converters are implemented by dual protocols of the initially given protocols which are to be interfaced. If the duals of those sub-protocols are implemented in separate modules, we can separate active modules and inactive modules on the fly since only one of the modules can be active at a time. The active/inactive state of a module can be monitored by the control signals that represent the execution of the protocol corresponding to the module. Power reduction can be achieved by dynamically suppressing the clock supply to inactive modules. To trade-off the power reduction rate against the area overhead, the module granularity must be properly chosen. For this purpose, we implement the duals of the atomic protocols in the same module if their state graphs share states except the initial state. Our experimental results show that this method provides significant savings in power consumption of between 18.4% and 92.1% with a 5.3% area overhead.