A System for Efficiently Self-Reconstructing 1(1/2)-Track Switch Torus Arrays

Tadayoshi HORITA  Itsuo TAKANAMI 

Publication
IEICE TRANSACTIONS on Information and Systems  Vol.E84-D  No.12  pp.1801-1809
Publication Date: 2001/12/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerance
Keyword: 
reconfiguration,  1(1/2)-track switch torus array,  fault tolerance,  wafer scale integration,  self-reconfigurable system, 

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Summary: 
A mesh-connected processor array consists of many similar processing elements (PEs), which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, it is necessary to consider some fault tolerant issues to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we introduce the 1(1/2)-track switch torus array by changing the connections in 1(1/2)-track switch mesh array, and we apply our approximate reconfiguration algorithm to the torus array. We describe the reconfiguration strategy for the 1(1/2)-track switch torus array and its realization using WSI, especially 3-dimensional realization. A hardware realization of the algorithm is proposed and simulation results about the array reliability are shown. These imply that a self-reconfigurable system with no host computer can be realized using our method, hence our method is effective in enhancing the run-time reliability as well as the fabrication-time yield of processor arrays.