An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core

Hiroshi SEGAWA  Yoshinori MATSUURA  Satoshi KUMAKI  Tetsuya MATSUMURA  Stefan SCOTZNIOVSKY  Shu MURAYAMA  Tetsuro WADA  Ayako HARADA  Eiji OHARA  Ken-ichi ASANO  Toyohiko YOSHIDA  Yasutaka HORIBA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E84-C   No.2   pp.202-211
Publication Date: 2001/02/01
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
video encoder,  MPEG-2,  media-processor,  audio encoder,  system encoder,  embedded software,  

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Summary: 
This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.