High RF Performance of 50-nm-Gate Lattice-Matched InAlAs/InGaAs HEMTs

Akira ENDOH  Yoshimi YAMASHITA  Masataka HIGASHIWAKI  Kohki HIKOSAKA  Takashi MIMURA  Satoshi HIYAMIZU  Toshiaki MATSUI 

Publication
IEICE TRANSACTIONS on Electronics  Vol.E84-C  No.10  pp.1328-1334
Publication Date: 2001/10/01
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Joint Special Issue on Heterostructure Microelectronics with TWHM 2000 (Topical Workshop on Heterostructure Microelectronics 2000))
Category: Hetero-FETs & Their Integrated Circuits
Keyword: 
InAlAs/InGaAs,  InP,  HEMT,  cutoff frequency,  low-temperature fabrication process, 

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Summary: 
We fabricated 50-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates by using a conventional process under low temperatures, below 300C, to prevent fluorine contamination and suppress possible diffusion of the Si-δ-doped sheet in the electron-supply layer, and measured the DC and RF performance of the transistors. The DC measurement showed that the maximum transconductance gm of a 50-nm-gate HEMT is about 0.91 S/mm. The cutoff frequency fT of our 50-nm-gate HEMT is 362 GHz, which is much higher than the values reported for previous 50-nm-gate lattice-matched HEMTs. The excellent RF performance of our HEMTs results from a shortening of the lateral extended range of charge control by the drain field, and this may have been achieved because the low-temperature fabrication process suppressed degradation of epitaxial structure.