Ultra Low Power Operation of Partially-Depleted SOI/CMOS Integrated Circuits

Koichiro MASHIKO  Kimio UEDA  Tsutomu YOSHIMURA  Takanori HIROTA  Yoshiki WADA  Jun TAKASOH  Kazuo KUBO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E83-C   No.11   pp.1697-1704
Publication Date: 2000/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
silicon on insulator (SOI),  complementary metal oxide semiconductor (CMOS),  emitter coupled logic (ECL),  

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Summary: 
Based on the partially-depleted, thin-film SOI/CMOS technology, the influence of reduced junction capacitance on the performance of the elementary gates and large scale gate array chip is reviewed. To further reduce the power consumption, SOI-specific device configurations, in which the body-bias is individually controlled, are effective in lowering the supply voltage and hence the power consumption while keeping the circuit speed. Two attempts are introduced: (1) DTMOS (Dynamic-Threshold MOS)/SOI to achieve ultra low-voltage and yet high-speed operation, and (2) ABB (Active-Body-Bias) MOS to enhance the current drive under the low supply voltage.