Design Optimization of VLSI Array Processor Architecture for Window Image Processing

Dongju LI  Li JIANG  Hiroaki KUNIEDA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E82-A   No.8   pp.1475-1484
Publication Date: 1999/08/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing)
image processing,  array processor,  window operation,  systolic array,  

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In this paper, we present a novel architecture named as Window-MSPA architecture which targets to window operations in image processing. We have previously developed a Memory Sharing Processor Array (MSPA) for fast array processing with regular iterative algorithms. Window-MSPA tries to optimize the data I/O ports and the number of processing elements so as to reduce hardware cost. The input scheme of image data is restricted to row by row input which simplifies the I/O architecture. Under this practical I/O restriction, the fastest processings are achieved. In this paper, we present the general Window-MSPA design methodology for wide variety of applications. As an practical application, we have already reported the design of MP@HL MPEG2 Motion Estimator LSI. Design formulas for Window-MSPA architecture are given for various size of window operations in image processing. Thus, the derived architecture is flexible enough to satisfy user's requirement for either area or speed.