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A DepthConstrained Technology Mapping Algorithm for LogicBlocks Composed of TreeStructured LUTs
Nozomu TOGAWA Koji ARA Masao YANAGISAWA Tatsuo OHTSUKI
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E82A
No.3
pp.473482 Publication Date: 1999/03/25
Online ISSN:
DOI:
Print ISSN: 09168508 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: technology mapping, logicblock, lookup table, logic depth,
Full Text: PDF(447.7KB)>>
Summary:
This paper proposes a fast depthconstrained technology mapping algorithm for logicblocks composed of treestructured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logicblocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound d_{c}. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

