Fault-Tolerant Meshes with Efficient Layouts

Toshinori YAMADA  Shuichi UENO 

Publication
IEICE TRANSACTIONS on Information and Systems  Vol.E81-D  No.1  pp.56-65
Publication Date: 1998/01/20
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
Keyword: 
meshes,  fault-tolerant graphs,  embeddings,  layouts,  wire length, 

Full Text: PDF

Summary: 
This paper presents a practical fault-tolerant architecture for mesh parallel machines that has t spare processors and has 2(t+2) communication links per processor while tolerating at most t+1 processor and link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most O(t).