The Phase Locked Loop for Clock Recovery Used in a Single-Chip 4-Channel 155Mb/s CMOS ATM Physical Layer Controller LSI

Takehiko NAKAO  Masanori KUWAHARA  Yasuo OHARA  Reiji ARIYOSHI  Toshihiko KITAZUME  Naoki SUGAWA  Takeshi OGAWARA  Satoshi ODA  Shoji NOMURA  Yuichi MIYAZAWA  Akira KANUMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E81-C   No.5   pp.746-749
Publication Date: 1998/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
PLL,  jitter,  ATM,  QPLC,  

Full Text: PDF(277.6KB)>>
Buy this Article




Summary: 
The Phase Locked Loop (PLL) for clock recovery used in a single chip 155. 52 Mb/s4-Ch CMOS LSI (QPLC) for SONET/SDH termination is described in this letter. This LSI is the first quad-channel ATM physical layer controller chip in which each channel has a clock recovery PLL achieving 55ps rms jitter, using current regulated constant amplitude differential VCO and the triple well structure.