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The Phase Locked Loop for Clock Recovery Used in a Single-Chip 4-Channel 155Mb/s CMOS ATM Physical Layer Controller LSI
Takehiko NAKAO Masanori KUWAHARA Yasuo OHARA Reiji ARIYOSHI Toshihiko KITAZUME Naoki SUGAWA Takeshi OGAWARA Satoshi ODA Shoji NOMURA Yuichi MIYAZAWA Akira KANUMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Issue on Multimedia, Network, and DRAM LSIs)
PLL, jitter, ATM, QPLC,
Full Text: PDF(277.6KB)>>
The Phase Locked Loop (PLL) for clock recovery used in a single chip 155. 52 Mb/s4-Ch CMOS LSI (QPLC) for SONET/SDH termination is described in this letter. This LSI is the first quad-channel ATM physical layer controller chip in which each channel has a clock recovery PLL achieving 55ps rms jitter, using current regulated constant amplitude differential VCO and the triple well structure.