Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis

Kazuhiro NAKAMURA  Shinji KIMURA  Kazuyoshi TAKAGI  Katsumasa WATANABE  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E81-A   No.12   pp.2515-2520
Publication Date: 1998/12/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
timing verification,  maximum delay analysis,  multiple clock operation,  false path,  

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This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.