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Intelligent Memory: An Architecture for Lock-Free Synchronization
Nakun SEONG Naihoon JUNG Byungho KIM Hyunsoo YOON
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/04/25
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Parallel and Distributed Supercomputing)
shared memory multiprocessor, synchronization, memory architecture,
Full Text: PDF(626.3KB)>>
This paper presents intelligent memory, a new memory architecture capable of providing efficient lock-free synchronization. In the intelligent memory, a sequence of operations on a shared object associated with that memory module can be processed without any intervention so that an environment for the synchronization can be provided by executing a critical section itself in that memory module. For this, we present a memory architecture for the intelligent memory having minimal instruction set and develop a progtramming model, called Critical Section Procedure (CSP), which consists of shared data structures and operations on them. Intelligent memory is intended to eliminate waste of processing time such as busy waiting in spin lock and the retry due to process contentions in existing lock-free synchronization schemes. Simulation results show that the intelligent memory provides better throughput compared with the spin lock and the existing lock-free synchronization schemes.