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CAM-Based Highly-Parallel Image Processing Hardware
Takeshi OGURA Mamoru NAKANISHI
IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
content addressable memory, CAM, image processing, highly-parallel processing,
Full Text: PDF(680KB)
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This paper describes content addressable memory (CAM) -based hardware that serves as a highly parallel, compact and real-time image-processing system. The novel concept of a highly-parallel integrated circuits and system (HiPIC), in which a large-capacity CAM tuned for parallel data processing is a key element, is introduced. Several hardware algorithms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effective for compact and real-time image processing. Two kinds of HiPIC-dedicated CAM have been developed. One is embedded on a 0.5-µm CMOS gate array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-µm CMOS full-custom CAM LSI tuned for parallel data processing. A fully-parallel 336-kbit CAM LSI has been successfully developed. The HiPIC concept and CAM-based hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.