A 3.2 GFLOPS Neural Network Accelerator

Shinji KOMORI  Yutaka ARIMA  Yoshikazu KONDO  Hirono TSUBOTA  Ken-ichi TANAKA  Kazuo KYUMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E80-C   No.7   pp.859-867
Publication Date: 1997/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: 
Keyword: 
neural network,  parallel processing,  SIMD,  LSI,  

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Summary: 
We have developed an SIMD-type neural-network processor (NEURO4) and its software environment. With the SIMD architecture, the chip executes 24 operations in a clock cycle and achieves 1.2 GFLOPS peak performance. An accelerator board, which contains four NEURO4 chips, achieves 3.2 GFLOPS. In this paper we describe features of the neural network chip, accelerator board, software environment and performance evaluation for several neural network models (LVQ, BP and Hopfield). The 3.2 GFLOPS neural network accelerator board demonstrates 1.7 GCPS and 261 MCUPS for Hopfield networks.