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Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH
Hideo MAEJIMA Masahiro KAINAGA Kunio UCHIYAMA
IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
RISC, architecture, low power, high speed, microprocessor,
Full Text: PDF(674.5KB)>>
This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.