Optimal Loop Bandwidth Design for Low Noise PLL Applications

Kyoohyun LIM  Seung Hee CHOI  Beomsup KIM  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E80-A   No.10   pp.1979-1985
Publication Date: 1997/10/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
optimal bandwidth,  PLL,  jitter,  low noise,  

Full Text: PDF(555.3KB)>>
Buy this Article




Summary: 
This paper presents a salient method to find an optimal bandwidth for low noise phase-locked loop (PLL) applications by analyzing a discrete-time model of charge-pump PLLs based on ring oscillator VCOs. The analysis shows that the timing jitter of the PLL system depends on the jitter in the ring oscillator and an accumulation factor which is inversely proportional to the bandwidth of the PLL. Further analysis shows that the timing jitter of the PLL system, however, proportionally depends on the bandwidth of the PLL when an external jitter source is applied. The analysis of the PLL timing jitter of both cases gives the clue to the optimal bandwidth design for low noise PLL applications, Simulation results using a C-language PLL model are compared with the theoretical predictions and show good agreement.