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Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors
Makoto IKEDA Kunihiro ASADA
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
low power, partitioned-bus architecture, variable-width-bus scheme, microprocessor,
Full Text: PDF(513.1KB)>>
We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.