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Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOSSRAM
IEICE TRANSACTIONS on Electronics Vol.E79-C No.3 pp.415-423
Publication Date: 1996/03/20
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
SRAM with logic gate,
Full Text: PDF(894.3KB)
A novel redundancy method suitable for an ultra-high-speed SRAM with logic gates is proposed. Fuse decoders are used to reduce the number of fuses, thus suppressing the access time degradation. This makes it possible to flip chip bond an SRAM with logic gates, which has a high pin count and operates at a very high frequency. To combine the new redundancy method and an ECL decoder circuit with a BiCMOS inverter, several schemes for disabling a defective cell and enabling a spare one are discussed. A 1-Mb ECL-CMOS SRAM with 120-k logic gates was fabricated using 0.3-µm BiCMOS technology. This SRAM consists of 16 RAM macros, and the RAM macro had an access time of only 0.65 ns. The access time degradation after repair was less than 50 ps.