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A Single Bridging Fault Location Technique for CMOS Combinational Circuits
IEICE TRANSACTIONS on Information and Systems Vol.E78-D No.7 pp.817-821
Publication Date: 1995/07/20
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Full Text: PDF(399.2KB)
A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs in deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates][the number of tests]2 bits, which is much smaller than that of the fault dictionary. The experimental results show that the number of possible bridging faults is reduced to less than 5 in several seconds, when using the tests to detect single stuck-at faults and considering only the bridging faults between physically adjacent nets.