
For FullText PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.

MultipleValued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation
Makoto HONDA Michitaka KAMEYAMA Tatsuo HIGUCHI
Publication
IEICE TRANSACTIONS on Electronics
Vol.E76C
No.3
pp.455462 Publication Date: 1993/03/25
Online ISSN:
DOI:
Print ISSN: 09168516 Type of Manuscript: Special Section PAPER (Special Issue on MultipleValued Integrated Circuits) Category: Keyword: multiplevalued MOS currentmode circuit, residue number system, latency, parallel processing, robot vision,
Full Text: PDF(737.7KB)>>
Summary:
The demand for highspeed image processing is obvious in many realworld computations such as robot vision. Not only high throughput but also small latency becomes an important factor of the performance, because of the requirement of frequent visual feedback. In this paper, a highperformance VLSI image processor based on the multiplevalued residue arithmetic circuit is proposed for such applications. Parallelism is hierarchically used to realize the highperformance VLSI image processor. First, spatially parallel architecture that is different from pipeline architecture is considered to reduce the latency. Secondly, residue number arithmetic is introduced. In the residue number arithmetic, data communication between the mod m_{i} arithmetic units is not necessary, so that multiple mod m_{i} arithmetic units can be completely separated to different chips. Therefore, a number of mod m_{i} multiply adders can be implemented on a single VLSI chip based on the modulusslice concept. Finally, each mod m_{i} arithmetic unit can be effectively implemented in parallel structure using the concept of a pseudoprimitive root and the multiplevalued currentmode circuit technology. Thus, it is made clear that the throughout use of parallelism makes the latency 1/3 in comparison with the ordinary binary implementation.

