For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation
Makoto HONDA Michitaka KAMEYAMA Tatsuo HIGUCHI
IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
multiple-valued MOS current-mode circuit, residue number system, latency, parallel processing, robot vision,
Full Text: PDF(737.7KB)>>
The demand for high-speed image processing is obvious in many real-world computations such as robot vision. Not only high throughput but also small latency becomes an important factor of the performance, because of the requirement of frequent visual feedback. In this paper, a high-performance VLSI image processor based on the multiple-valued residue arithmetic circuit is proposed for such applications. Parallelism is hierarchically used to realize the high-performance VLSI image processor. First, spatially parallel architecture that is different from pipeline architecture is considered to reduce the latency. Secondly, residue number arithmetic is introduced. In the residue number arithmetic, data communication between the mod mi arithmetic units is not necessary, so that multiple mod mi arithmetic units can be completely separated to different chips. Therefore, a number of mod mi multiply adders can be implemented on a single VLSI chip based on the modulus-slice concept. Finally, each mod mi arithmetic unit can be effectively implemented in parallel structure using the concept of a pseudoprimitive root and the multiple-valued current-mode circuit technology. Thus, it is made clear that the throughout use of parallelism makes the latency 1/3 in comparison with the ordinary binary implementation.