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Computational Ordering of Digital Networks under Pipeline Constraints and Its Application to DSP Compilers
Nobuhiko SUGINO Seiji OHBI Akinori NISHIHARA
IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/12/25
Print ISSN: 0000-0000
Type of Manuscript: Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)
Category: Digital Signal Processing
Full Text: PDF(643.1KB)>>
To reduce users' load in writing programs for DSPs (Digital Signal Processors), especially those with several pipeline stages, an improved search algorithm is proposed which determines the computational order for a given digital network and generates codes automatically. To search an effective order, a new representation of the precedence form is proposed. A new technique to generate effective codes is also presented. Taking the DSP architecture into account, the method re-allocates the computational order to reduce blanks in the microcodes. These methods are applied to the compilers for µPD77230, µPD7720 and TMS32010/20, which give relatively effective codes.