A Statistical Study of Two-Dimensional Random-Logic Placement and Applications to MOS Layout--Statistical Models--

Kang Min CHUNG  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E71   No.1   pp.56-63
Publication Date: 1988/01/25
Online ISSN: 
Print ISSN: 0000-0000
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 


Full Text: PDF(689.9KB)
>>Buy this Article


Summary: 
This paper presents several statistical and empirical approaches to estimating circuit area required for laying out a given number of random-logic gates. The approaches are developed for MOS layout methods in which terminals for load and driver devices account for independent wiring tracks. For placements and interconnections, two statistical models involving (a) linear superposition of one-dimensional placements and (b) uniform, diffused connections of terminals on a wiring track, are introduced. Block width dependent wiring track requirements are determined by incorporating one-dimensional logic partitioning across the block. An empirical relationship for the spatial partitioning is established from a collection of placements done with a manual layout method.