Limit Cycle-Free 2-D Separable Denominator Digital Filters under Any Constant Input Conditions

Masayuki KAWAMATA  Tatsuo HIGUCHI  

Publication
IEICE TRANSACTIONS (1976-1990)   Vol.E70   No.4   pp.373-375
Publication Date: 1987/04/25
Online ISSN: 
DOI: 
Print ISSN: 0000-0000
Type of Manuscript: LETTER
Category: Circuit Theory
Keyword: 


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Summary: 
In order to suppress constant input limit cycles in 2-D separable denominator digital filters, bias cancel realizations are proposed by modifying 2-D separable denominator digital filters free of zero imput limit cycles.