VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks

David ALEDO  Benjamin CARRION SCHAFER  Félix MORENO  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E102-D   No.3   pp.512-521
Publication Date: 2019/03/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2018EDP7142
Type of Manuscript: PAPER
Category: Computer System
Keyword: 
VHDL,  SystemC,  high-level synthesis (HLS),  artificial neural network (ANN),  

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Summary: 
This paper describes the advantages and disadvantages observed when describing complex parameterizable Artificial Neural Networks (ANNs) at the behavioral level using SystemC and at the Register Transfer Level (RTL) using VHDL. ANNs are complex to parameterize because they have a configurable number of layers, and each one of them has a unique configuration. This kind of structure makes ANNs, a priori, challenging to parameterize using Hardware Description Languages (HDL). Thus, it seems intuitively that ANNs would benefit from the raise in level of abstraction from RTL to behavioral level. This paper presents the results of implementing an ANN using both levels of abstractions. Results surprisingly show that VHDL leads to better results and allows a much higher degree of parameterization than SystemC. The implementation of these parameterizable ANNs are made open source and are freely available online. Finally, at the end of the paper we make some recommendation for future HLS tools to improve their parameterization capabilities.