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A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip
Pil-Ho LEE Young-Chan JANG
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/06/01
Online ISSN: 1745-1337
Type of Manuscript: Special Section LETTER (Special Section on Circuits and Systems)
transmission buffer chip, LVDS, SLVS, MIPI D-PHY, FPGA-based frame generator,
Full Text: PDF(1.7MB)>>
A 3Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.