Critical Path Based Microarchitectural Bottleneck Analysis for Out-of-Order Execution

Teruo TANIMOTO  Takatsugu ONO  Koji INOUE  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E102-A   No.6   pp.758-766
Publication Date: 2019/06/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E102.A.758
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems)
Category: 
Keyword: 
critical path analysis,  Out-of-Order processor,  CPI stack,  bottleneck analysis,  

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Summary: 
Correctly understanding microarchitectural bottlenecks is important to optimize performance and energy of OoO (Out-of-Order) processors. Although CPI (Cycles Per Instruction) stack has been utilized for this purpose, it stacks architectural events heuristically by counting how many times the events occur, and the order of stacking affects the result, which may be misleading. It is because CPI stack does not consider the execution path of dynamic instructions. Critical path analysis (CPA) is a well-known method to identify the critical execution path of dynamic instruction execution on OoO processors. The critical path consists of the sequence of events that determines the execution time of a program on a certain processor. We develop a novel representation of CPCI stack (Cycles Per Critical Instruction stack), which is CPI stack based on CPA. The main challenge in constructing CPCI stack is how to analyze a large number of paths because CPA often results in numerous critical paths. In this paper, we show that there are more than ten to the tenth power critical paths in the execution of only one thousand instructions in 35 benchmarks out of 48 from SPEC CPU2006. Then, we propose a statistical method to analyze all the critical paths and show a case study using the benchmarks.