Design and Analysis of Approximate Multipliers with a Tree Compressor

Tongxin YANG  Tomoaki UKEZONO  Toshinori SATO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E102-A   No.3   pp.532-543
Publication Date: 2019/03/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E102.A.532
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
approximate computing,  approximate tree compressor,  high speed multiplier,  low power multiplier,  small area multiplier,  

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Many applications, such as image signal processing, has an inherent tolerance for insignificant inaccuracies. Multiplication is a key arithmetic function for many applications. Approximate multipliers are considered an efficient technique to trade off energy relative to performance and accuracy for the error-tolerant applications. Here, we design and analyze four approximate multipliers that demonstrate lower power consumption and shorter critical path delay than the conventional multiplier. They employ an approximate tree compressor that halves the height of the partial product tree and generates a vector to compensate accuracy. Compared with the conventional Wallace tree multiplier, one of the evaluated 8-bit approximate multipliers reduces power consumption and critical path delay by 36.9% and 38.9%, respectively. With a 0.25% normalized mean error distance, the silicon area required to implement the multiplier is reduced by 50.3%. Our multipliers outperform the previously proposed approximate multipliers relative to power consumption, critical path delay, and design area. Results from two image processing applications also demonstrate that the qualities of the images processed by our multipliers are sufficiently accurate for such error-tolerant applications.