A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Fara ASHIKIN  Masaki HASHIZUME  Hiroyuki YOTSUYANAGI  Shyue-Kung LU  Zvi ROTH  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E101-D   No.8   pp.2053-2063
Publication Date: 2018/08/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2018EDP7093
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
3D stacked IC,  open defects,  design-for-testability,  through-silicon via,  electrical interconnect test,  

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Summary: 
A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.