A General Low-Cost Fast Hybrid Reconfiguration Architecture for FPGA-Based Self-Adaptive System

Rui YAO  Ping ZHU  Junjie DU  Meiqun WANG  Zhaihe ZHOU  

IEICE TRANSACTIONS on Information and Systems   Vol.E101-D   No.3   pp.616-626
Publication Date: 2018/03/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2017EDP7231
Type of Manuscript: PAPER
Category: Computer System
adaptive system,  hybrid reconfiguration,  evolvable hardware (EHW),  bitstream relocation,  discrepancy configuration,  

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Evolvable hardware (EHW) based on field-programmable gate arrays (FPGAs) opens up new possibilities towards building efficient adaptive system. State of the art EHW systems based on virtual reconfiguration and dynamic partial reconfiguration (DPR) both have their limitations. The former has a huge area overhead and circuit delay, and the later has slow configuration speed and low flexibility. Therefore a general low-cost fast hybrid reconfiguration architecture is proposed in this paper, which merges the high flexibility of virtual reconfiguration and the low resource cost of DPR. Moreover, the bitstream relocation technology is introduced to save the bitstream storage space, and the discrepancy configuration technology is adopted to reduce reconfiguration time. And an embedded RAM core is adopted to store bitstreams which accelerate the reconfiguration speed further. The proposed architecture is evaluated by the online evolution of digital image filter implemented on the Xilinx Virtex-6 FPGA development board ML605. And the experimental results show that our system has lower resource overhead, higher operating frequency, faster reconfiguration speed and less bitstream storage space in comparison with the previous works.