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NEST: Towards Extreme Scale Computing Systems
Yunfeng LU Huaxi GU Xiaoshan YU Kun WANG
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2018/11/01
Online ISSN: 1745-1361
Type of Manuscript: LETTER
Category: Information Network
high-performance computing, optical interconnects, optical switches, network topology,
Full Text: PDF(309KB)
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High-performance computing (HPC) has penetrated into various research fields, yet the increase in computing power is limited by conventional electrical interconnections. The proposed architecture, NEST, exploits wavelength routing in arrayed waveguide grating routers (AWGRs) to achieve a scalable, low-latency, and high-throughput network. For the intra pod and inter pod communication, the symmetrical topology of NEST reduces the network diameter, which leads to an increase in latency performance. Moreover, the proposed architecture enables exponential growth of network size. Simulation results demonstrate that NEST shows 36% latency improvement and 30% throughput improvement over the dragonfly on an average.