Quantized Decoder Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for a Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor

Nobuaki KOBAYASHI  Tadayoshi ENOMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E101-C   No.8   pp.671-679
Publication Date: 2018/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E101.C.671
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
dynamic voltage and frequency scaling (DVFS),  low power dissipation,  CMOS,  motion estimation processor,  

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Summary: 
To completely utilize the advantages of dynamic voltage and frequency scaling (DVFS) techniques, a quantized decoder (QNT-D) was developed. The QNT-D generates a quantized signal processing quantity (Q) using a predicted signal processing quantity (M). Q is used to produce the optimum frequency (opt.fc) and the optimum supply voltage (opt.VD) that are proportional to Q. To develop a DVFS controlled motion estimation (ME) processor, we used both the QNT-D and a fast ME algorithm called A2BC (Adaptively Assigned Breaking-off Condition) to predict M for each macro-block (MB). A DVFS controlled ME processor was fabricated using 90-nm CMOS technology. The total power dissipation (PT) of the processor was significantly reduced and varied from 38.65 to 99.5 µW, only 3.27 to 8.41 % of PT of a conventional ME processor, depending on the test video picture.