Column-Parallel ADCs for CMOS Image Sensors and Their FoM-Based Evaluations

Shoji KAWAHITO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E101-C   No.7   pp.444-456
Publication Date: 2018/07/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E101.C.444
Type of Manuscript: INVITED PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
CMOS image sensor,  column-parallel ADC,  cyclic ADC,  delta-sigma modulation,  single-slope ADC,  SAR ADC,  figure of merit,  

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Summary: 
This paper reviews architectures and topologies for column-parallel analog-to-digital converters (ADCs) used for CMOS image sensors (CISs) and discusses the performance of CISs using column-parallel ADCs based on figures-of-merit (FoM) with considering noise models which behave differently at low/middle and high pixel-rate regions. Various FoM considering different performance factors are defined. The defined FoM are applied to surveyed data on reported CISs using column-parallel ADCs which are categorized into 4 types; single slope, SAR, cyclic and delta-sigma ADCs. The FoM defined by (noise)2(power)/(pixel-rate) separately for low/middle and high pixel-rate regions well explains the frontline of the CIS' performance in all the pixel rates. Using the FoM defined by (noise)2(power)/(intrascene dynamic range)(pixel-rate), the effectiveness of recently-reported techniques for extended-dynamic-range CISs is clarified.