A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate

Motofumi NAKANISHI  Shintaro IZUMI  Mio TSUKAHARA  Hiroshi KAWAGUCHI  Hiromitsu KIMURA  Kyoji MARUMOTO  Takaaki FUCHIKAMI  Yoshikazu FUJIMORI  Masahiko YOSHIMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E101-C   No.4   pp.233-242
Publication Date: 2018/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E101.C.233
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
adaptive sampling,  normally off computing,  physical activity classification,  sensor fusion,  SoC,  

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Summary: 
This paper presents an algorithm for a physical activity (PA) classification and metabolic equivalents (METs) monitoring and its System-on-a-Chip (SoC) implementation to realize both power reduction and high estimation accuracy. Long-term PA monitoring is an effective means of preventing lifestyle-related diseases. Low power consumption and long battery life are key features supporting the wider dissemination of the monitoring system. As described herein, an adaptive sampling method is implemented for longer battery life by minimizing the active rate of acceleration without decreasing accuracy. Furthermore, advanced PA classification using both the heart rate and acceleration is introduced. The proposed algorithms are evaluated by experimentation with eight subjects in actual conditions. Evaluation results show that the root mean square error with respect to the result of processing with fixed sampling rate is less than 0.22[METs], and the mean absolute error is less than 0.06[METs]. Furthermore, to minimize the system-level power dissipation, a dedicated SoC is implemented using 130-nm CMOS process with FeRAM. A non-volatile CPU using non-volatile memory and a flip-flop is used to reduce the stand-by power. The proposed algorithm, which is implemented using dedicated hardware, reduces the active rate of the CPU and accelerometer. The current consumption of the SoC is less than 3-µA. And the evaluation system using the test chip achieves 74% system-level power reduction. The total current consumption including that of the accelerometer is 11.3-µA on average.