Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting

Toru NAKURA  Tsukasa KAGAYA  Tetsuya IIZUKA  Kunihiro ASADA  

IEICE TRANSACTIONS on Electronics   Vol.E101-C   No.4   pp.218-223
Publication Date: 2018/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E101.C.218
Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
quick start PLL,  phase and frequency presetting,  

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This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18µm standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105µm×870µm silicon area.