Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology


IEICE TRANSACTIONS on Electronics   Vol.E101-C   No.1   pp.78-81
Publication Date: 2018/01/01
Online ISSN: 1745-1353
Type of Manuscript: PAPER
Category: Electronic Circuits
3D NAND,  design for manufacturability,  energy efficient,  yield improvement,  

Full Text: PDF(649.4KB)
>>Buy this Article

This paper discusses design challenges and possible solutions for 3D NAND. A 3D NAND array inherently has a larger parasitic capacitance and thereby critical area in terms of product yield. To mitigate such issues associated with 3D NAND technology, array control and divided array architecture for improving reliability and yield and for reducing area overhead, program time, energy per bit and array noise are proposed.