Development of a Low Standby Power Six-Transistor CMOS SRAM Employing a Single Power Supply

Nobuaki KOBAYASHI  Tadayoshi ENOMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E101-C   No.10   pp.822-830
Publication Date: 2018/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E101.C.822
Type of Manuscript: PAPER
Category: Electronic Circuits
Keyword: 
CMOS,  SRAM,  static-noise margin,  standby power dissipation,  leakage current,  Self-controllable Voltage Level (SVL) circuit,  

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Summary: 
We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, not only to expand both “write” and “read” stabilities, but also to achieve a low stand-by power and data holding capability in a single low power supply, 90-nm, 2-kbit, six-transistor CMOS SRAM. The SVL circuit can adaptively lower and higher the word-line voltages for a “read” and “write” operation, respectively. It can also adaptively lower and higher the memory cell supply voltages for the “write” and “hold” operations, and “read” operation, respectively. This paper focuses on the “hold” characteristics and the standby power dissipations (PST) of the developed SRAM. The average PST of the developed SRAM is only 0.984µW, namely, 9.57% of that (10.28µW) of the conventional SRAM at a supply voltage (VDD) of 1.0V. The data hold margin of the developed SRAM is 0.1839V and that of the conventional SRAM is 0.343V at the supply voltage of 1.0V. An area overhead of the SVL circuit is only 1.383% of the conventional SRAM.