An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines

Nobutaro SHIBATA  Mitsuo NAKAMURA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E101-A   No.8   pp.1185-1196
Publication Date: 2018/08/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E101.A.1185
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
ATE,  delay-locked loop,  digital-to-time converter,  linearity error,  on the fly,  plain CMOS logic,  timing jitter,  timing vernier,  

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Summary: 
Timing vernier (i.e., digital-to-time converter) is a key component of the pin-electronics circuit board installed in automated digital-VLSI test equipment, and it is used to create fine delays of less than one-cycle time of a clock signal. This paper presents a new on-the-fly (timing-) jitter suppression technique which makes it possible to use low-power plain-CMOS-logic-based timing verniers. Using a power-compensation line installed at the poststage of the digitally variable delay line, we make every pulse (used as a timing signal) consume a fixed amount of electric energy independent of the required delay amount. Since the power load of intrapowerlines is kept constantly, the jitter increase in the situation of changing the required delay amount on the fly is suppressed. On the basis of the concept, a 10-ns span, 125-MHz timing-vernier macro was designed and fabricated with a CMOS process for logic VLSIs. Every macro installed in a real-time timing-signal generator VLSI achieved the required timing resolution of 31.25ps with a linearity error within 15ps. The on-the-fly jitter was successfully suppressed to a random jitter level (<26ps p-p).