A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution

Pietro NANNIPIERI  Daniele DAVALLE  Luca FANUCCI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E101-A   No.7   pp.1120-1122
Publication Date: 2018/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E101.A.1120
Type of Manuscript: LETTER
Category: Digital Signal Processing
Keyword: 
VLSI,  8b10b,  parallel,  encoding,  

Full Text: PDF(246.8KB)
>>Buy this Article


Summary: 
8B/10B is an encoding technique largely used in different communication protocols, with several advantages such as zero DC bias. In the last years transmission rates have grown rapidly, thus the need of encoders with better performance in terms of throughput, area and power consumption raised rapidly. In this article we will present and discuss the architecture of two symbols parallel encoder, comparing it with a classical pipelined solution.