Applying an SMT Solver to Coverage-Driven Design Verification

Kiyoharu HAMAGUCHI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E101-A   No.7   pp.1053-1056
Publication Date: 2018/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E101.A.1053
Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
RTL verification,  coverage-driven verification,  SAT solver,  SMT solver,  automated testbench,  

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Summary: 
Simulation-based verification of hardware designs, in particular, register-transfer-level (RTL) designs, has been widely used, and has been one of the major bottlenecks in design processes. One of the approaches is coverage-driven verification, of its target is improvement of some metric called coverage. In a prior work of ours, we have proposed a coverage-driven verification using both randomly generated simulation patterns and patterns generated by a SAT (satisfiability) solver, and have shown its effectiveness. In this paper, we extend this approach with an SMT (satisfiability modulo theory) solver, which can handle arithmetic relations among integer, floating-point or bit-vector variables. Experimental results show that the more arithmetic modules are included, the more an SMT-based method gets superior to the method using only a SAT solver.