A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories

Tatsuro KOJO  Masashi TAWADA  Masao YANAGISAWA  Nozomu TOGAWA  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E101-A   No.7   pp.1045-1052
Publication Date: 2018/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E101.A.1045
Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
non-volatile memory,  bit-write-reducing,  error-correcting codes,  clustering conditions,  S-bit flip conditions,  S-bound graph,  cluster graph,  relaxed REC code,  

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Non-volatile memories are a promising alternative to memory design but data stored in them still may be destructed due to crosstalk and radiation. The data stored in them can be restored by using error-correcting codes but they require extra bits to correct bit errors. One of the largest problems in non-volatile memories is that they consume ten to hundred times more energy than normal memories in bit-writing. It is quite necessary to reduce writing bits. Recently, a REC code (bit-write-reducing and error-correcting code) is proposed for non-volatile memories which can reduce writing bits and has a capability of error correction. The REC code is generated from a linear systematic error-correcting code but it must include the codeword of all 1's, i.e., 11…1. The codeword bit length must be longer in order to satisfy this condition. In this letter, we propose a method to generate a relaxed REC code which is generated from a relaxed error-correcting code, which does not necessarily include the codeword of all 1's and thus its codeword bit length can be shorter. We prove that the maximum flipping bits of the relaxed REC code is still limited theoretically. Experimental results show that the relaxed REC code efficiently reduce the number of writing bits.