A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element

Saki TAJIMA  Nozomu TOGAWA  Masao YANAGISAWA  Youhua SHI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E101-A   No.7   pp.1025-1034
Publication Date: 2018/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E101.A.1025
Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
soft error,  low-power,  latch,  C-element,  

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Summary: 
To deal with the reliability issue caused by soft errors, this paper proposed a low power soft error hardened latch (SHC) design using a novel Schmitt-Trigger-based C-element for reliable low power applications. Unlike state-of-the-art soft error tolerant latches that are usually based on hardware redundancy with large area overhead and high power consumption, the proposed SHC latch is implemented through double-sampling and node-checking using a novel Schmitt-Trigger-based C-element, which can help to reduce the area overhead and the corresponding power consumption as well. The evaluation results show that the total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 20.35% and 82.96% power reduction can be achieved when compared to the conventional unhardened C2MOS latch and the existing soft error tolerant HiPeR design, respectively.