For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation
Toshinori HOSOKAWA Atsushi HIRAI Yukari YAMAUCHI Masayuki ARAI
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2017/09/01
Online ISSN: 1745-1361
Type of Manuscript: PAPER
Category: Dependable Computing
low power, test generation, capture safe test vectors, test vector synthesis, unsafe faults,
Full Text: PDF(1.4MB)
>>Buy this Article
In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the response for a test vector is captured by flip-flops results in excessive voltage drops, known as IR-drops, which may cause significant capture-induced yield loss. In low capture power test generation, the test vectors that violate capture power constraints in an initial test set are defined as capture-unsafe test vectors, while faults that are detected solely by capture-unsafe test vectors are defined as unsafe faults. It is necessary to regenerate the test vectors used to detect unsafe faults in order to prevent unnecessary yield losses. In this paper, we propose a new low capture power test generation method based on fault simulation that uses capture-safe test vectors in an initial test set. Experimental results show that the use of this method reduces the number of unsafe faults by 94% while requiring just 18% more additional test vectors on average, and while requiring less test generation time compared with the conventional low capture power test generation method.