Automatic Generation System for Multiple-Valued Galois-Field Parallel Multipliers

Rei UENO  Naofumi HOMMA  Takafumi AOKI  

IEICE TRANSACTIONS on Information and Systems   Vol.E100-D   No.8   pp.1603-1610
Publication Date: 2017/08/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.2016LOP0010
Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
GF arithmetic circuits,  formal design,  parallel multipliers,  automatic generation,  multiple-valued logic,  

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This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG). The proposed system employs a graph-based circuit description called the GF Arithmetic Circuit Graph (GF-ACG). First, we present an extension of the GF-ACG to handle GF(pm) (p≥3) arithmetic circuits, which can be efficiently implemented by multiple-valued logic circuits in addition to the conventional binary circuits. We then show the validity of the generation system through the experimental design of GF(pm) multipliers for different p-values. In addition, we evaluate the performance of three types of GF(2m) multipliers and typical GF(pm) multipliers (p≥3) empirically generated by our system. We confirm from the results that the proposed system can generate a variety of GF parallel multipliers, including practical multipliers over GF(pm) having extension degrees greater than 128.