Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests

Hiroshi IWATA  Nanami KATAYAMA  Ken'ichi YAMAGUCHI  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E100-D   No.6   pp.1182-1189
Publication Date: 2017/06/01
Online ISSN: 1745-1361
Type of Manuscript: Special Section PAPER (Special Section on Formal Approach)
Category: Formal techniques
Keyword: 
redundancy identification,  transition faults,  broadside scan test,  formal verification and functional equivalence,  

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Summary: 
In accordance with Moore's law, recent design issues include shortening of time-to-market and detection of delay faults. Several studies with respect to formal techniques have examined the first issue. Using the equivalence checking, it is possible to identify whether large circuits are equivalent or not in a practical time frame. With respect to the latter issue, it is difficult to achieve 100% fault efficiency even for transition faults in full scan designs. This study involved proposing a redundant transition fault identification method using equivalence checking. The main concept of the proposed algorithm involved combining the following two known techniques, 1. modeling of a transition fault as a stuck-at fault with temporal expansion and 2. detection of a stuck-at fault by using equivalence checking tools. The experimental results indicated that the proposed redundant identification method using a formal approach achieved 100% fault efficiency for all benchmark circuits in a practical time even if a commercial ATPG tool was unable to achieve 100% fault efficiency for several circuits.