Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Junji YAMADA  Ushio JIMBO  Ryota SHIOYA  Masahiro GOSHIMA  Shuichi SAKAI  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E100-D   No.4   pp.822-837
Publication Date: 2017/04/01
Online ISSN: 1745-1361
Type of Manuscript: PAPER
Category: Computer System
Keyword: 
superscalar processor,  register file,  multibanking,  

Full Text: PDF(3.2MB)
>>Buy this Article


Summary: 
The region that includes the register file is a hot spot in high-performance cores that limits the clock frequency. Although multibanking drastically reduces the area and energy consumption of the register files of superscalar processor cores, it suffers from low IPC due to bank conflicts. Our skewed multistaging drastically reduces not the bank conflict probability but the pipeline disturbance probability by the second stage. The evaluation results show that, compared with NORCS, which is the latest research on a register file for area and energy efficiency, a proposed register file with 18 banks achieves a 39.9% and 66.4% reduction in circuit area and in energy consumption, while maintaining a relative IPC of 97.5%.